The present invention relates generally to FRAMs (ferroelectric random access memories), and more particularly to improved circuits and methods for preventing corruption of data in FRAMs due to power interruptions.
FRAMs (also known as FeRAMs) are generally considered to be “non-volatile” because they continue to store data even if their operating power is interrupted. FRAM by nature is characterized by “destructive readout”, which means that any time a FRAM memory cell undergoes a read operation its stored information is destroyed, and therefore the corresponding readout information must be rewritten back into that FRAM memory cell.
The power applied to a FRAM may be “interrupted”, i.e., may undergo a transition to a level outside of an acceptable range, because of a disruption in the main power being applied to a system that contains the FRAM. The power applied to the FRAM also may be interrupted in some cases if there is an external short-circuiting of a package pin or pad to ground, or possibly if someone succeeds in hacking into a system containing the FRAM in such a way as to cause an interruption in the power supplied to the FRAM. Data stored in the FRAM will be corrupted and permanently lost if ordinary memory read and write operations occur while the power applied to the FRAM is being interrupted. As an example, if the operating power supply voltage VFRAM applied to the FRAM and associated read/write/rewrite circuitry is equal to 1.8 volts, and if during a power interruption VFRAM falls below approximately 1.6 volts, data involved in any on-going read and write operations will be corrupted.
Referring to FIG. 1A, a known system 1A including an “embedded” FRAM 2 also includes digital core logic 3 that is coupled by means of a bidirectional bus 11 to FRAM 2. Digital core logic 3 is coupled to an external digital system (not shown) by means of a bidirectional data and control bus 14. FRAM 2 and digital core logic 3 both are powered by a supply voltage VCORE which may also be referred to as VFRAM, on conductor 4-1. Digital core logic 3 is coupled by a digital bus 13 to a clock generation and control circuit 10. Conductor 4-1 is coupled to a conductive integrated circuit package pad or pin 5 on the integrated circuit chip on which FRAM memory system 1A is fabricated. The desired supply voltage VFRAM applied to digital core logic 3 and FRAM 2 is generated on conductive pad 5 by means of a LDO (Low Drop Out) regulator circuit 7, the output of which is connected to a conductor 4-3. LDO voltage regulator 7 includes an operational amplifier 8 having its (+) input coupled to a reference voltage VREF and its (−) input coupled by conductor 9 to the junction between a voltage divider including resistor R1 and resistor R2. The output of amplifier 8 is connected by conductor 4-3 to apply a regulated output voltage VLDO across resistive voltage divider R1,R2. The regulated output voltage VLDO thus is applied to conductive pad 5, which also is connected to FRAM 2 and digital core logic 3 by conductor 4-1. Conductive pad 5 also is connected by conductor 4-2 to a large external bypass capacitor CEXT.
In this example, amplifier 8 is powered by a main supply voltage VSUPPLY, which is applied to a conductive bonding pad 6. VREF may be equal to 1.8 volts, so VLDO is regulated to 1.8 volts. Therefore, the FRAM supply voltage VFRAM, which is also the supply voltage for digital core logic 3, is also equal to 1.8 V. CEXT is very large, and may for example be equal to 2.2 microfarads. A suitable power interrupt detection circuit 15 detects the voltage VFRAM=VCORE on conductor 4-1. If a power interruption is detected, power interrupt detection circuit 15 communicates with digital core logic 3 via bus 11, causing it to operate so as to (1) prevent any new FRAM read, write, or rewrite operations from being started, and (2) to complete any already-started read and write operations within a predetermined time interval after the detection of the FRAM power interruption, to thereby prevent corruption of FRAM data.
One problem with the system shown in FIG. 1A is that whenever VSUPPLY is interrupted, the 1.8 volt memory supply voltage VLDO=VFRAM will also be interrupted, causing corruption of any FRAM data involved in any new or ongoing read, write, or rewrite operation in FRAM 2. Another problem is that whenever the external conductive pad or pin 5 is inadvertently short-circuited to ground, the 1.8 volt memory supply voltage VFRAM is likely to fall below 1.6 V, likely causing corruption of data involved in any on-going or subsequent read and write operations in FRAM 2 during the power interruption.
To overcome the foregoing data corruption problems in this example, the external bypass capacitor CEXT must maintain the supply voltage VFRAM coupled to both digital core logic 3 and FRAM 2 above 1.6 volts for a sufficiently long interval, for example at least 200 ns (nanoseconds), to allow completion of all on-going FRAM read and write operations. During that 200 ns interval, digital core logic 3 and FRAM 2 drain a large amount of current from external bypass capacitor CEXT, which must be sufficiently large to maintain VFRAM above 1.6 volts to prevent corruption of data in FRAM 2 during the 200 ns interval.
Referring to FIG. 1B, the illustrated system 1B is essentially the same as the system 1A shown in FIG. 1A except that conductive pin 5 is omitted and the output voltage VLDO of LDO regulator 1A is connected directly by conductor 4-3 to the supply voltage terminals of FRAM 2 and digital core logic 3. In this case, the external storage capacitor CINT of FIG. 1A is omitted, and instead an internal storage capacitor CINT is coupled between conductor 4-3 and ground and is included on the integrated circuit chip on which system 1B is fabricated. Unfortunately, this technique is very costly because the required very large internal storage voltage capacitor CINT requires a great deal of integrated circuit chip area.
Thus, there is an unmet need for an improved circuit and method for preventing corruption of data stored in a FRAM during an unexpected supply voltage interruption.
There also is an unmet need for a more efficient circuit and method for preventing corruption of data stored in a FRAM during an unexpected supply voltage interruption.
There also is an unmet need for a less costly circuit and method for preventing corruption of data stored in a FRAM during an unexpected supply voltage interruption.
There also is an unmet need for an improved, more efficient circuit and method for preventing corruption of data stored in a FRAM during an unexpected supply voltage interruption, wherein the circuit and method require substantially less integrated circuit chip area than in the prior art.